The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Performance analysis of embedded software using implicit path enumeration
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Java Virtual Machine Specification
Java Virtual Machine Specification
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Design for Timing Predictability
Real-Time Systems
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Design and Implementation of an Efficient Stack Machine
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
WCET analysis for a Java processor
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
High-Performance Embedded Computing: Architectures, Applications, and Methodologies
High-Performance Embedded Computing: Architectures, Applications, and Methodologies
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
The coming wave of multithreaded chip multiprocessors
International Journal of Parallel Programming
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
JEOPARD: Java environment for parallel real-time development
JTRES '08 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems
Time-predictable memory arbitration for a Java chip-multiprocessor
JTRES '08 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems
Predictable programming on a precision timed architecture
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A Single-Path Chip-Multiprocessor System
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
RTTM: real-time transactional memory
Proceedings of the 2010 ACM Symposium on Applied Computing
Cyclic executive for safety-critical Java on chip-multiprocessors
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
Object oriented machine learning with a multicore real-time Java processor: short paper
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
The embedded Java benchmark suite JemBench
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
Scheduling real-time garbage collection on uniprocessors
ACM Transactions on Computer Systems (TOCS)
Temporal isolation on multiprocessing architectures
Proceedings of the 48th Design Automation Conference
Real-time wait-free queues using micro-transactions
Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems
ejIP: a TCP/IP stack for embedded Java
Proceedings of the 9th International Conference on Principles and Practice of Programming in Java
Safety-critical Java with cyclic executives on chip-multiprocessors
Concurrency and Computation: Practice & Experience
About 15 years of real-time Java
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
On the scalability of time-predictable chip-multiprocessing
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
Implementing a ring-based real-time capable network using a multithreaded Java processor
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
Data cache organization for accurate timing analysis
Real-Time Systems
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A hard real-time capable multi-core SMT processor
ACM Transactions on Embedded Computing Systems (TECS)
GALS-CMP: chip-multiprocessor for GALS embedded systems
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Chip-multiprocessor hardware locks for safety-critical Java
Proceedings of the 11th International Workshop on Java Technologies for Real-time and Embedded Systems
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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Chip-multiprocessors are an emerging trend for embedded systems. In this article, we introduce a real-time Java multiprocessor called JopCMP. It is a symmetric shared-memory multiprocessor, and consists of up to eight Java Optimized Processor (JOP) cores, an arbitration control device, and a shared memory. All components are interconnected via a system on chip bus. The arbiter synchronizes the access of multiple CPUs to the shared main memory. In this article, three different arbitration policies are presented, evaluated, and compared with respect to their real-time and average-case performance: a fixed priority, a fair-based, and a time-sliced arbiter. Tasks running on different CPUs of a chip-multiprocessor (CMP) influence each others' execution times when accessing a shared memory. Therefore, the system needs an arbiter that is able to limit the worst-case execution time of a task running on a CPU, even though tasks executing simultaneously on other CPUs access the main memory. Our research shows that timing analysis is in fact possible for homogeneous multiprocessor systems with a shared memory. The timing analysis of tasks, executing on the CMP using time-sliced memory arbitration, leads to viable worst-case execution time bounds. The time-sliced arbiter divides the memory access time into equal time slots, one time slot for each CPU. This memory arbitration scheme allows for a calculation of upper bounds of Java application worst-case execution times, depending on the number of CPUs, the time slot size, and the memory access time. Examples of worst-case execution time calculation are presented, and the analyzed results of a real-world application task are compared to measured execution time results. Finally, we evaluate the tradeoffs when using a time-predictable solution compared to using average-case optimized chip-multiprocessors, applying three different benchmarks. These experiments are carried out by executing the programs on the CMP prototype.