Time-predictable memory arbitration for a Java chip-multiprocessor
JTRES '08 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems
Reliable performance analysis of a multicore multithreaded system-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
Dataflow models for shared memory access latency analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
A Single-Path Chip-Multiprocessor System
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
Worst-case response time analysis of resource access models in multi-core systems
Proceedings of the 47th Design Automation Conference
Bounding the shared resource load for the performance analysis of multiprocessor systems
Proceedings of the Conference on Design, Automation and Test in Europe
Real-time performance analysis of multiprocessor systems with shared memory
ACM Transactions on Embedded Computing Systems (TECS)
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A hard real-time capable multi-core SMT processor
ACM Transactions on Embedded Computing Systems (TECS)
Predictable two-level bus arbitration for heterogeneous task sets
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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in general, the predictability of real-time applications imple- mented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system's communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks' WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we propose, for the first time, an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures.