Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Memory arbitration and cache management in stream-based systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hard Real-time Computing Systems: Predictable Scheduling Algorithms And Applications (Real-Time Systems Series)
Design for Timing Predictability
Real-Time Systems
Integrated analysis of communicating tasks in MPSoCs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Modelling run-time arbitration by latency-rate servers in dataflow graphs
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploring locking & partitioning for predictable shared caches on multi-cores
Proceedings of the 45th annual Design Automation Conference
Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration
RTCSA '08 Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach
ECRTS '08 Proceedings of the 2008 Euromicro Conference on Real-Time Systems
A Priority-Based Budget Scheduler with Conservative Dataflow Model
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
A new data flow analysis model for TDM
Proceedings of the tenth ACM international conference on Embedded software
Flexible filters in stream programs
ACM Transactions on Embedded Computing Systems (TECS)
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Performance analysis of applications in multi-core platforms is challenging because of temporal interference while accessing shared resources. Especially, memory arbiters introduce a non-constant delay which significantly influences the execution time of a task. In this paper, we selected a priority-based budget scheduler as memory arbiter which bounds temporal interference by construction and is well suited for bursty service provision. While existing performance analysis approaches assume a constant memory access latency leading to high overestimation, we propose in this paper a conservative data flow model for this scheduler, in which the history of memory accesses is considered. In a case study with an MP3-decoder for an ARM7 processor, we show that using a constant memory access latency for the selected scheduler results in an overestimation of three order of magnitudes. Compared to simulation, the proposed data flow model shows an overestimation of less than 3% while in previous work the overestimation was up to 104%. Furthermore, the proposed approach improves the performance by about 20% compared to a time-division-multiplex scheduler.