Dataflow models for shared memory access latency analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Proceedings of the 47th Design Automation Conference
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis
Proceedings of the Conference on Design, Automation and Test in Europe
The CompSOC design flow for virtual execution platforms
Proceedings of the 10th FPGAworld Conference
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The convergence of application domains in new systems-on-chip (SoC) results in systems with many applications with a mix of soft and hard real-time requirements. To reduce cost, resources, such as memories and interconnect, are shared between applications. However, resource sharing introduces interference between the sharing applications, making it difficult to satisfy their real-time requirements. Existing arbiters do not efficiently satisfy the requirements of applications in SoCs, as they either couple rate or allocation granularity to latency, or cannot run at high speeds in hardware with a low-cost implementation.The contribution of this paper is an arbiter called Credit-Controlled Static-Priority (CCSP), consisting of a rate regulator and a static-priority scheduler. The rate regulator isolates applications by regulating the amount of provided service in a way that decouples allocation granularity and latency. The static-priority scheduler decouples latency and rate, such that low latency can be provided to any application, regardless of the allocated rate. We show that CCSP belongs to the class of latency-rate servers and guarantees the allocated rate within a maximum latency, as required by hard real-time applications. We present a hardware implementation of the arbiter in the context of a DDR2 SDRAM controller. An instance with six ports running at 200 MHz requires an area of 0.0223 mm2in a 90 nm CMOS process.