Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends

  • Authors:

  • Benny Akesson;Po-Chun Huang;Fabien Clermidy;Denis Dutoit;Kees Goossens;Yuan-Hao Chang;Tei-Wei Kuo;Pascal Vivet;Drew Wingard

  • Affiliations:

  • Eindhoven University of Technology, Eindhoven, Netherlands;National Taiwan University, Taipei, Taiwan Roc;CEA LETI, Grenoble, France;CEA LETI, Grenoble, France;Eindhoven University of Technology, Eindhoven, Netherlands;Academia Sinica, Taipei, Taiwan Roc;National Taiwan University, Academia Sinica, Taipei, Taiwan Roc;CEA LETI, Grenoble, France;Sonics Inc., San Jose, USA

  • Venue:
  • CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
  • Year:
  • 2011

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Abstract

Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power.