Scheduling Parallel Computations
Journal of the ACM (JACM)
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Introduction to Algorithms
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Online resource management in a multiprocessor with a network-on-chip
Proceedings of the 2007 ACM symposium on Applied computing
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Signal Processing
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modular performance analysis of cyclic dataflow graphs
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Simultaneous budget and buffer size computation for throughput-constrained task graphs
Proceedings of the Conference on Design, Automation and Test in Europe
Constrained global scheduling of streaming applications on MPSoCs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
MPSoC programming using the MAPS compiler
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Hard-real-time scheduling of data-dependent tasks in embedded streaming applications
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Designing next-generation real-time streaming systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A new data flow analysis model for TDM
Proceedings of the tenth ACM international conference on Embedded software
Managing latency in embedded streaming applications under hard-real-time scheduling
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
CADSE: communication aware design space exploration for efficient run-time MPSoC management
Frontiers of Computer Science: Selected Publications from Chinese Universities
Maximum-throughput mapping of SDFGs on multi-core SoC platforms
Journal of Parallel and Distributed Computing
A reconfigurable real-time SDRAM controller for mixed time-criticality systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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This paper proposes a scheduling strategy and an automatic scheduling flow that enable the simultaneous execution of multiple hard-real-time dataflow jobs. Each job has its own execution rate and starts and stops independently from other jobs, at instants unknown at compile-time, on a multiprocessor system-on-chip. We show how a combination of Time-Division Multiplex (TDM) and static-order scheduling can be modeled as additional nodes and edges on top of the dataflow representation of the job using Single-Rate Dataflow semantics to enable tight worst-case temporal analysis. We also propose algorithms to find combined TDM/static order schedules for jobs that guarantee a requested minimum throughput and maximum latency, while minimizing the usage of processing resources. We illustrate the usage of these techniques for a combination of Wireless LAN and TD-SCDMA radio jobs running on a prototype Software-Defined Radio platform.