Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Managing dynamic concurrent tasks in embedded real-time multimedia systems
Proceedings of the 15th international symposium on System Synthesis
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design & Test
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Throughput Analysis of Synchronous Data Flow Graphs
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Efficient design space exploration for application specific systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Embedded Computing Systems (TECS)
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Run-time management of a MPSoC containing FPGA fabric tiles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICLP '08 Proceedings of the 24th International Conference on Logic Programming
Throughput Constraint for Synchronous Data Flow Graphs
CPAIOR '09 Proceedings of the 6th International Conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems
Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the Conference on Design, Automation and Test in Europe
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management
PAAP '11 Proceedings of the 2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming
PAAP '11 Proceedings of the 2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs
Proceedings of the 49th Annual Design Automation Conference
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip (MPSoC). Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisfy their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources' status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration (CADSE) techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results.