Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
A design framework to efficiently explore energy-delay tradeoffs
Proceedings of the ninth international symposium on Hardware/software codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
TriMedia CPU64 Design Space Exploration
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Cache optimization for embedded processor cores: An analytical approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient design space exploration of high performance embedded out-of-order processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A genetic algorithm for channel routing in vlsi circuits
Evolutionary Computation
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
Performance assessment of multiobjective optimizers: an analysis and review
IEEE Transactions on Evolutionary Computation
A GA-based design space exploration framework for parameterized system-on-a-chip platforms
IEEE Transactions on Evolutionary Computation
Approximation Capabilities of Hierarchical Fuzzy Systems
IEEE Transactions on Fuzzy Systems
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A genetic approach to standard cell placement using meta-genetic parameter optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-granularity sampling for simulating concurrent heterogeneous applications
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-processor system-on-chip design space exploration based on multi-level modeling techniques
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Proceedings of the 47th Design Automation Conference
Decision-theoretic design space exploration of multiprocessor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture exploration for efficient data transfer and storage in data-parallel applications
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
Microprocessors & Microsystems
Supervised design space exploration by compositional approximation of Pareto sets
Proceedings of the 48th Design Automation Conference
A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Divide and conquer high-level synthesis design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
ACM Transactions on Embedded Computing Systems (TECS)
Boosting design space explorations with existing or automatically learned knowledge
MMB'12/DFT'12 Proceedings of the 16th international GI/ITG conference on Measurement, Modelling, and Evaluation of Computing Systems and Dependability and Fault Tolerance
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models
Proceedings of the Conference on Design, Automation and Test in Europe
Design space pruning through hybrid analysis in system-level design space exploration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
CADSE: communication aware design space exploration for efficient run-time MPSoC management
Frontiers of Computer Science: Selected Publications from Chinese Universities
Exploiting domain knowledge in system-level MPSoC design space exploration
Journal of Systems Architecture: the EUROMICRO Journal
Design-space exploration and runtime resource management for multicores
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
ASAM: Automatic architecture synthesis and application mapping
Microprocessors & Microsystems
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A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip (SoC) platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a SoC platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration (DSE) in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy Systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized SoC platform based on a parameterized VLIW processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established DSE approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time.