Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A register file and scheduling model for application specific processor synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
Journal of VLSI Signal Processing Systems
Design Challenges for New Application-Specific Processors
IEEE Design & Test
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
Performing Scheduling and Storage Optimization Simultaneously Using Genetic Algorithms
MWSCAS '98 Proceedings of the 1998 Midwest Symposium on Systems and Circuits
PARELEC '00 Proceedings of the International Conference on Parallel Computing in Electrical Engineering
Fuzzy decision making in embedded system design
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Efficient design space exploration for application specific systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
Proceedings of the 45th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Custom Processor Core Construction from C Code
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Fundamentals of Digital Logic with VHDL Design with CD-ROM
Fundamentals of Digital Logic with VHDL Design with CD-ROM
A family of compact genetic algorithms for intrinsic evolvable hardware
IEEE Transactions on Evolutionary Computation
A genetic algorithm for the design space exploration of datapaths during high-level synthesis
IEEE Transactions on Evolutionary Computation
A formal approach to the scheduling problem in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As the growth of system complexity rapidly increases, the gap between Electronic System Level (ESL) and the Register Transfer Level (RTL) must be filled. Currently, Very Large Scale Integration (VLSI) and System-on-Chip (SoC) designs are multi-objective in nature, requiring simultaneous fulfillment of multiple parameters. Extensive research on Design Space Exploration (DSE) problems and synthesis of an application specific processor (ASP) design have been done until now but none of the prior works have focused explicitly on integrating a fast multi-objective architecture exploration mechanism with the architectural synthesis stages to formalize the design methodology of an application specific processor in case of multiple objectives. This paper proposes a design methodology of a multi-objective application specific processor by integrating an efficient multi-objective (area occupied, execution time and power consumption) exploration approach with the architecture synthesis process, useful for portable devices and many high end applications. The formalized steps of the design methodology for the ASP guarantees the designer an error free approach to design the system with strict limitations on compound operational constraints. The results of implementation of the designed ASP using the proposed design methodology in FPGA and ASIC have also been shown.