Scheduling and binding algorithms for high-level synthesis

Authors:
P. G. Paulin;J. P. Knight
Affiliations:
BNR, PO. Box 35 11, Stn. "C", Ottawa, Canada K1Y 4H7;Carleton Univ., Dept. of Electronics, Ottawa, Canada K1S 5B6
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques by making use of a global priority function. A new design-space exploration technique, which combines this algorithm with an existing one based on time constraints, is also presented.A second algorithm is used for register and bus allocation to satisfy two criteria: the minimization of interconnect costs as well as the final register (bus) cost. A clique partitioning approach is used where the clique graph is pruned using interconnect affinities between register (bus) pairs. Examples from current literature were chosen to illustrate the algorithms and to compare them with four existing systems.