Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A timing analysis of level-clocked circuitry
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Valid clocking in wavepipelined circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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