Statistical failure analysis of system timing
IBM Journal of Research and Development
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Computer Design
Introduction to VLSI Systems
Statistical techniques of timing verification
DAC '83 Proceedings of the 20th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Double-Edge-Triggered Flip-Flops
IEEE Transactions on Computers
Circuit implementation of high-speed pipeline systems
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Characterization of branch and data dependencies on programs for evaluating pipeline performance
IEEE Transactions on Computers
IEEE Transactions on Computers
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for library-specific sizing of combinational logic
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
IBM Enterprise System/9000 clock system: a technology and system perspective
IBM Journal of Research and Development
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
On testing wave pipelined circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Rephasing: a transformation technique for the manipulation of timing constraints
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
A unified approach in the analysis of latches and flip-flops for low-power systems
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
IEEE Design & Test
Salphasic Distribution of Clock Signals for Synchronous Systems
IEEE Transactions on Computers
Clocking and Clocked Storage Elements in Multi-GHz Environment
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
A novel high-speed sense-amplifier-based flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 15.07 |
A key element (one is tempted to say the heart) of most digital systems is the clock. Its period determines the rate at which data are processed, and so should be made as small as possible, consistent with reliable operation.