The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Computer Design
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Design for testability and diagnosis in a VLSI CMOS System/370 processor
IBM Journal of Research and Development
The design of the M3S: a multiported shared-memory multiprocessor
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Properties of Generalized Branch and Combine Clock Networks
IEEE Transactions on Parallel and Distributed Systems
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A clock-tuning circuit for system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Stability analysis of active clock deskewing systems using a control theoretic approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Theory of Generalized Branch and Combine Clock Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Hybrid design for testability combining scan and clock line control and method for test generation
ITC'94 Proceedings of the 1994 international conference on Test
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Provides a framework for understanding system timing and then describes how the computer clock system executes the timing specifications. He examines clock generation and the construction of clock-distribution networks, which are integral to any clock system. Examples from contemporary high-speed systems highlight several common methods of clock generation, distribution, and tuning. Tight control of system clock skew is stressed.