Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Shift Register Sequences
IEEE Design & Test
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Standard-cell-based design methodology for high-performance support chips
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Testing the Enterprise IBM System/390" Multi Processor
ITC '97 Proceedings of the 1997 IEEE International Test Conference
| Hi-index | 0.00 |