Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
IBM Journal of Research and Development
Simulation of embedded memories by defective hashing
IBM Journal of Research and Development
Design for testability and diagnosis in a VLSI CMOS System/370 processor
IBM Journal of Research and Development
Aliasing errors in linear automata used as multiple-input signature analyzers
IBM Journal of Research and Development
IBM Journal of Research and Development
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Statistical Resistance to Detection (Digital Circuits Testing)
IEEE Transactions on Computers
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
Recursive Pseudoexhaustive Test Pattern Generation
IEEE Transactions on Computers
Test pattern generation based on arithmetic operations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Aliasing Computation Using Fault Simulation with Fault Dropping
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
IEEE Transactions on Computers
IEEE Transactions on Computers
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
IEEE Transactions on Computers
On Linear Dependencies in Subspaces of LFSR-Generated Sequences
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Programmable BIST Space Compactors
IEEE Transactions on Computers
On the Use of Counters for Reproducing Deterministic Test Sets
IEEE Transactions on Computers
GigaHertz MUX-DEMUX Chip with HF BIST
Analog Integrated Circuits and Signal Processing - Special issue: selected articles from the 1995 NORCHIP seminar
Efficient random testing with global weights
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A Test Methodology for High Performance MCMs
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Multichip Module Diagnosis by Product-Code Signatures
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Delay Test Generation: A Hardware Perspective
Journal of Electronic Testing: Theory and Applications
Module Level Weighted Random Patterns
Journal of Electronic Testing: Theory and Applications
Frequency-domain compatibility in digital filter BIST
DAC '97 Proceedings of the 34th annual Design Automation Conference
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Reduced Latch Count Shift Registers
Journal of Electronic Testing: Theory and Applications
Partial Symmetry in Cellular Automata Rule Vectors
Journal of Electronic Testing: Theory and Applications
Salvaging Test Windows in BIST Diagnostics
IEEE Transactions on Computers
Random Pattern Testability of Memory Control Logic
IEEE Transactions on Computers
Determining Aliasing Probabilities in BIST by Counting Strings
Journal of Electronic Testing: Theory and Applications
Synthesis of BIST hardware for performance testing of MCM interconnections
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
A Bist Scheme for Non-Volatile Memories
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
On-Chip Weighted Random Patterns
Journal of Electronic Testing: Theory and Applications
2-by-n$n$ Hybrid Cellular Automata with Regular Configuration: Theory and Application
IEEE Transactions on Computers
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Tree-Structured Linear Cellular Automata and Their Applications in BIST
Journal of Electronic Testing: Theory and Applications
Cost and benefit models for logic and memory BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On Random Pattern Testability of Cryptographic VLSI Cores
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Stochastic sequential machine synthesis with application to constrained sequence generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Distributed BIST Architecture to Combat Delay Faults
Journal of Electronic Testing: Theory and Applications
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
IEEE Transactions on Computers
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
A novel reseeding technique for accumulator-based test pattern generation
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Cellular automata as a built in self test structure
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Novel Test Pattern Generators for Pseudoexhaustive Testing
IEEE Transactions on Computers
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
Automatic generation and compaction of March Tests for memory arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures
IEEE Transactions on Computers
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems
Journal of Electronic Testing: Theory and Applications
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
Boundary Scan with Built-In Self-Test
IEEE Design & Test
Scan-Path Architecture for Pseudorandom Testing
IEEE Design & Test
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test
IEEE Design & Test
Design and Test of an Integrated Cryptochip
IEEE Design & Test
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Reducing Hardware with Fuzzy Multiple Signature Analysis
IEEE Design & Test
Using VHDL for Board Level Simulation
IEEE Design & Test
On-Chip IDDQ Testing in the AE11 Fail-Stop Controller
IEEE Design & Test
Using a Soft Core in a SoC Design: Experiences with picoJava
IEEE Design & Test
System-on-Chip Testability Using LSSD Scan Structures
IEEE Design & Test
Economics of Built-in Self-Test
IEEE Design & Test
IEEE Design & Test
A Multiple Seed Linear Feedback Shift Register
IEEE Transactions on Computers
Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks
IEEE Transactions on Computers
Notes on Multiple Input Signature Analysis
IEEE Transactions on Computers
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
Counter-Based Compaction: Delay and Stuck-Open Faults
IEEE Transactions on Computers
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST
IEEE Transactions on Computers
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Theory of Extended Linear Machines
IEEE Transactions on Computers
IEEE Design & Test
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel combinational testability analysis by considering signal correlation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A distributed BIST technique for diagnosis of MCM interconnections
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new framework for generating optimal March tests for memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Modeling Fault Coverage of Random Test Patterns
Journal of Electronic Testing: Theory and Applications
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Generator choices for delay test
ATS '95 Proceedings of the 4th Asian Test Symposium
Module level weighted random patterns
ATS '95 Proceedings of the 4th Asian Test Symposium
A programmable multiple-sequence generator for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
Fast fault simulation for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
Pseudo-exhaustive word-oriented DRAM testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Multiplicative Window Generators of Pseudo-random Test Vectors
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Deterministic Test Pattern Reproduction by a Counter
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
BIST for Embedded Word-Oriented DRAM
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Impact of Partial Reset on Fault Independent Testing and BIST
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Design Of A Universal BIST (UBIST) Structure
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Obtaining High Fault Coverage with Circular BIST Via State Skipping
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Random pattern testability of memory control logic
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
10.2 Design of Phase Shifters for BIST Applications
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
10.3 Distributed Generation of Weighted Random Patterns
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
DFT Advances in Motorola's Next-Generation 74xx PowerPC" Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On-Line and Off-Line Test of Airborne Digital Systems: a Reliability Study
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Bridging the Gap Between Embedded Test and ATE
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Self Test Architecture for Testing Complex Memory Structures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Structure Verification of Logical BIST: Problems and Solutions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Tackling Test Trade-offs from Design, Manufacturing to Market using Economic Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Building Block BIST Methodology for SOC Designs: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Method to Enhance the Fault Coverage Obtained by Output Response Comparison of Identical Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TEST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
GRAAL: a Tool for Highly Dependable SRAMs Generation
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Addressing Early Design-For-Test Synthesis in a Production Environment
ITC '97 Proceedings of the 1997 IEEE International Test Conference
DS-LFSR: A New BIST TPG for Low Heat Dissipation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
TREE-STRUCTURED LINEAR CELLULAR AUTOMATA AND THEIR APPLICATIONS AS PRPGS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
FAULT DIAGNOSIS IN-SCAN-BASED BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Scan Latch Design for Delay Test
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
On Accumulator-Based Bit-Serial Test Response Compaction Schemes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
High-Level Synthesis Methodology for On-Line Testability Optimization
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Emulating static faults using a Xilinx based emulator
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Testing strategies for networks on chip
Networks on chip
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An On-Line BISTed SRAM IP Core
ITC '99 Proceedings of the 1999 IEEE International Test Conference
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Compacting Test Responses for Deeply Embedded SoC Cores
IEEE Design & Test
Achieving At-Speed Structural Test
IEEE Design & Test
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
IEEE Transactions on Computers
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Scan Latch Design for Test Applications
Journal of Electronic Testing: Theory and Applications
Challenges and directions for testing IC
Integration, the VLSI Journal
Planar High Performance Ring Generators
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
How to reduce aliasing in linear analog testing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Theory and application of cellular automata for pattern classification
Fundamenta Informaticae - Special issue on cellular automata
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A unified method for phase shifter computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
IEEE Transactions on Computers
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors
IEEE Transactions on Dependable and Secure Computing
IEEE Transactions on Computers
High Performance Dense Ring Generators
IEEE Transactions on Computers
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
DFT timing design methodology for at-speed BIST
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A core generator for arithmetic cores and testing structures with a network interface
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Computer Science and Technology
L-CBF: a low-power, fast counting bloom filter architecture
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the conference on Design, automation and test in Europe
Journal of Integrated Design & Process Science
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Investigating some special sequence lengths generated in an external exclusive-NOR type LFSR
Computers and Electrical Engineering
A 12-Gb/s DEMUX Implemented with SiGe high-speed FPGA circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Antirandom testing: a distance-based approach
VLSI Design
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
L-CBF: a low-power, fast counting bloom filter architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation study of the functioning of LFSR for grade 4 irreducible polynomials
SEPADS'09 Proceedings of the 8th WSEAS International Conference on Software engineering, parallel and distributed systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Operating system scheduling for efficient online self-test in robust systems
Proceedings of the 2009 International Conference on Computer-Aided Design
On-line testing of lab-on-chip using reconfigurable digital-microfluidic compactors
International Journal of Parallel Programming
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A scalable test structure for multicore chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Self-test techniques for crypto-devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Built-in system test and fault location
ITC'94 Proceedings of the 1994 international conference on Test
Aliasing-free signature analysis for RAM BIST
ITC'94 Proceedings of the 1994 international conference on Test
GLFSR: a new test pattern generator for built-in-self-test
ITC'94 Proceedings of the 1994 international conference on Test
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
Efficient test response compression for multiple-output circuits
ITC'94 Proceedings of the 1994 international conference on Test
Transparent memory testing for pattern sensitive faults
ITC'94 Proceedings of the 1994 international conference on Test
Concurrent engineering with DFT in the digital system: a parallel process
ITC'94 Proceedings of the 1994 international conference on Test
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits
ITC'94 Proceedings of the 1994 international conference on Test
Boundary scan with cellular-based built-in self-test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On multiple fault coverage and aliasing probability measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Identification of failing tests with cycling registers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Using scan technology for debug and diagnostics in a workstation environment
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Scan diagnostic strategy for the series 10000 PRISM workstation
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Altera max plus II development environment in fault simulation and test implementation of embedded
IWDC'04 Proceedings of the 6th international conference on Distributed Computing
Implementation of embedded cores-based digital devices in JBits java simulation environment
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
Increasing embedding probabilities of RPRPs in RIN based BIST
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Efficient and reliable low-power backscatter networks
Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
Theory and Application of Cellular Automata For Pattern Classification
Fundamenta Informaticae - Cellular Automata
Efficient and reliable low-power backscatter networks
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Built-in generation of functional broadside tests using a fixed hardware structure
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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