Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Comparative Analysis of Different Implementations of Multiple-Input Signature Analyzers
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability
IEEE Transactions on Parallel and Distributed Systems
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Built-in Self Test Based on Multiple On-Chip Signature Checking
Journal of Electronic Testing: Theory and Applications
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Notes on Multiple Input Signature Analysis
IEEE Transactions on Computers
Generalized Hopfield Neural Network for Concurrent Testing
IEEE Transactions on Computers
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
A Note on Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Counter-Based Compaction: Delay and Stuck-Open Faults
IEEE Transactions on Computers
On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers
IEEE Transactions on Computers
Aliasing Error for a Mask ROM Built-In Self-Test
IEEE Transactions on Computers
IEEE Transactions on Computers
| Hi-index | 15.02 |
Single and multiple multiple-input-signature-register (MISR) aliasing probability expressions are presented for arbitrary test lengths. A framework, based on algebraic codes, is developed for the analysis and synthesis of MISR-based test response compressors for BIST. This framework is used to develop closed-form expressions for the aliasing probability of MISR for arbitrary test length. An error model, based on q-ary symmetric channel, is proposed using more realistic assumptions. Results are presented that provide the weight distributions for q-ary codes (q=2/sup m/, where the circuit under test has m outputs). These results are used to compute the aliasing probability for the MISR compression technique for arbitrary test lengths. This result is extended to compression using two different MISRs. It is shown that significant improvements can be obtained by using two signature analyzers instead of one. The weight distribution of a class of codes of arbitrary length is also given.