Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
On switching policies for modular redundancy fault-tolerant computing systems
IEEE Transactions on Computers
Coverage Modeling for Dependability Analysis of Fault-Tolerant Systems
IEEE Transactions on Computers
Fault Detection in Combinational Networks by Reed-Muller Transforms
IEEE Transactions on Computers
Performance Analysis of a Generalized Concurrent Error Detection Procedure
IEEE Transactions on Computers
Computational Complexity of Controllability/Observability Problems for Combinational Circuits
IEEE Transactions on Computers
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Neural networks: an introduction
Neural networks: an introduction
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits
IEEE Transactions on Computers
| Hi-index | 14.98 |
The use of generalized Hopfield neural networks in designing the checking circuitry of a concurrent testable circuit is discussed. The aliasing probability, a measure for evaluating the performance of the checking circuitry, is provided. It is shown how, by using spectral techniques based on the Reed-Muller transform, the aliasing probability can be expressed as a function of the Reed-Muller coefficients. Therefore, obtaining the checking circuitry means selecting a set of Reed-Muller spectral coefficients, with fewer elements than a given bound, that minimizes the aliasing probability. To apply the neural networks to design the checking circuitry for concurrent testing, the aliasing probability has been used as an energy function, and the Hopfield neural network has been modified to have an associated energy function with any type of polynomial dependence on the processor states.