Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs
IEEE Transactions on Computers
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
IEEE Transactions on Computers
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
Model for transient and permanent error-detection and fault-isolation coverage
IBM Journal of Research and Development
Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
Probability to Achieve TSC Goal
IEEE Transactions on Computers
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
Optimal Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
Self-Testing Embedded Two-Rail Checkers
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Journal of Electronic Testing: Theory and Applications
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Generalized Hopfield Neural Network for Concurrent Testing
IEEE Transactions on Computers
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
Journal of Electronic Testing: Theory and Applications
Generalized modular design of testable m-out-of-n code checker
ATS '95 Proceedings of the 4th Asian Test Symposium
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Design of Embedded Self-Testing Checkers for t-UED and BUED Codes
Journal of Electronic Testing: Theory and Applications
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes"
Journal of Electronic Testing: Theory and Applications
Self-Testing Embedded Borden t-UED Code Checkers for t=2kq-1 with q=2m-1
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A fault-tolerant permutation network modulo arithmetic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new design for a 驴self-checking checker for nonencoded multiinput combinational circuits. A built-in testing method is also stressed. The proposed checker, called a generalized prediction checker (GPC), has an extended and generalized form of conventional parity prediction checkers, and includes a duplication checker as a special case. A parity check matrix H imparts arbitrary error detection ability to the new GPC. The GPC is made perfectly self-testing by applying a new method that adds one extra input to the cascaded multiinput comparator and to the cascaded XOR tree circuit in the GPC. This extra input may take any value during normal operation. The 驴self-checking GPC is implemented for specific circuit examples and verified. For these examples, the 驴self-checking GPC's show 100 percent fault coverage for single stuck faults in both the circuit under check and the checker itself. Using this checker, the built-in testing method taking advantage of the checker's automatic fault detection ability is shown to be suitable for testing combinational circuits.