A fault-tolerant permutation network modulo arithmetic processor

Authors:
Ming-Bo Lin;A. Yavuz Oruç
Affiliations:
Electronic Engineering Department, National Taiwan Institute of Technology, Taipei, Taiwan;Electrical Engineering Department, University of Maryland, College Park, MD
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

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Abstract

Conventional fault-tolerant modulo arithmetic processors rely on the properties of a residue number system with L redundant moduli to detect up to L/2 errors. In this paper, we propose a new scheme that combines r-out-of-s. residue codes with Berger codes to concurrently detect any number of module errors without any redundant moduli. In addition, this scheme can tolerate L faults if L redundant moduli are used, and has the property of graceful degradation when the number of faulty moduli exceeds L. Finally, it is shown that the added cost for fault tolerance is much less than those were reported earlier in the literature.