The Design of Error Checkers for Self-Checking Residue Number Arithmetic

Authors:
W. K. Jenkins
Affiliations:
Department of Electrical Engineering and the Coordinated Science Laboratory, University of Illinois
Venue:
IEEE Transactions on Computers
Year:
1983

Citing 4
Cited 2

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Residue Number Scaling and Other Operations Using ROM Arrays

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Error Detection and Correction by Product Codes in Residue Number Systems

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Error Correction in Residue Arithmetic

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Computation as estimation: a general framework for robustness and energy efficiency in SoCs

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A fault-tolerant permutation network modulo arithmetic processor

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Abstract

During the last few years residue number (RNS) arithmetic has gained increasing importance for providing high speed fault tolerant performance in dedicated digital signal processors. One factor that has limited the use of redundant RNS theory in practice is the hardware complexity of the error checker. This paper presents a mathematical analysis of the error correction algorithm which suggests a new design with considerably reduced hardware complexity. A hardward architecture for a high speed pipelined error checker is proposed.