Floating-Point Arithmetic Algorithms in the Symmetric Residue Number System
IEEE Transactions on Computers
Sign Detection in Residue Number Systems
IEEE Transactions on Computers
A Note on Fast Base Extension for Residue Number Systems with Three Moduli
IEEE Transactions on Computers
Remarks on Base Extension for Modular Arithmetic
IEEE Transactions on Computers
A state-of-the-art SIMD two-dimensional FFT array processor
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The Design of Error Checkers for Self-Checking Residue Number Arithmetic
IEEE Transactions on Computers
An Autoscale Residue Multiplier
IEEE Transactions on Computers
An Overflow-Free Residue Multiplier
IEEE Transactions on Computers
Sign Detection and Implicit-Explicit Conversion of Numbers in Residue Arithmetic
IEEE Transactions on Computers
A VLSI Residue Arithmetic Multiplier
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
A Residue Number System Implementation of the LMS Algorithm Using Optical Waveguide Circuits
IEEE Transactions on Computers
Fast scaling in the residue number system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 15.01 |
Over the last two decades there has been considerable interest in the implementation of digital computer elements using hardware based on the residue number system. This paper considers implementing such systems with arrays of look-up tables placed in high density read-only memories. The type of system discussed is restricted to one in which the only operations are addition, subtraction, multiplication, and scaling by a predetermined constant. Special attention is given to the scaling algorithm, and two different scaling algorithms are developed.