A state-of-the-art SIMD two-dimensional FFT array processor

Authors:
Mehrad Yasrebi;G. J. Lipovski
Affiliations:
Communications Products Division, IBM Corporation, Reseacrh Triangle Park, NC;Department of Electrical Engineering, The University of Texas at Austin
Venue:
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Year:
1984

Citing 13
Cited 0

An Adaptation of the Fast Fourier Transform for Parallel Processing

Journal of the ACM (JACM)
A Sampler of Circuit Switching Networks

Computer
Parallel Processing with the Perfect Shuffle

IEEE Transactions on Computers
Design Considerations for Single-Chip Computers of the Future

IEEE Transactions on Computers
On the Mapping Problem

IEEE Transactions on Computers
Residue Number Scaling and Other Operations Using ROM Arrays

IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks

IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks

IEEE Transactions on Computers
Implementation of FFT Structures Using the Residue Number System

IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition

IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks

IEEE Transactions on Computers
Packet Switching Interconnection Networks for Modular Systems

Computer
The multidimensional access memory in STARAN

IEEE Transactions on Computers - Special issue on parallel processors and processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

A novel implementation of a Two-dimensional FFT array processor is given. The reasons for its superior performance is the one-to-one and onto mapping of the problem communications topology onto the interconnection network, VLSI-based implementation, a proper choice for the number system, multiple-parallelism, and the use of packet-switching as opposed to circuit switching. A performance comparison also presented.