A connecting network with fault tolerance capabilities
IEEE Transactions on Computers - The MIT Press scientific computation series
Permutations on Illiac IV-Type Networks
IEEE Transactions on Computers
Evaluation of On-Chip Static Interconnection Networks
IEEE Transactions on Computers
An analytical model for a class of processor-memory interconnection networks
IEEE Transactions on Computers
A Characterization and Analysis of Parallel Processor Interconnection Networks
IEEE Transactions on Computers
The effect of inter-PE communication network configuration on the performance of array computers
ANSS '92 Proceedings of the 25th annual symposium on Simulation
Dynamic Iterative Method for Fast Network Partitioning
HPCN Europe 2000 Proceedings of the 8th International Conference on High-Performance Computing and Networking
Parallel Edge Coloring of a Tree on a Mesh Connected Computer
TCS '00 Proceedings of the International Conference IFIP on Theoretical Computer Science, Exploring New Frontiers of Theoretical Informatics
A state-of-the-art SIMD two-dimensional FFT array processor
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Parallel Algorithms to Set Up the Benes Permutation Network
IEEE Transactions on Computers
Parallel Processing Approaches to Image Correlation
IEEE Transactions on Computers
IEEE Transactions on Computers
Binary Trees and Parallel Scheduling Algorithms
IEEE Transactions on Computers
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
On the Number of Permutations Performable by the Augmented Data Manipulator Network
IEEE Transactions on Computers
Optimal BPC Permutations on a Cube Connected SIMD Computer
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
SIMD Machines and Cellular d-Graph Automata
IEEE Transactions on Computers
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
Routing Schemes for the Augmented Data Manipulator Network in an MIMD System
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
Information and Computation
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Shuffling with the Illiac and PM2I SIMD Networks
IEEE Transactions on Computers
A Classification of Cube-Connected Networks with a Simple Control Scheme
IEEE Transactions on Computers
Camera setup optimization for optical tracking in virtual environments
EGVE'06 Proceedings of the 12th Eurographics conference on Virtual Environments
| Hi-index | 15.04 |
A formal mathematical model of single instruction stream-multiple data stream (SIMD) machines is defined. It is used as a basis for analyzing various types of interconnection networks that have been discussed in the literature. The networks are evaluated in terms of the lower and upper bounds on the time required for each of the networks discussed to simulate the other networks. SIMD machine algorithms are presented as proofs of the upper time bounds on these simulation tasks. These simulations are used to demonstrate techniques for proving the correctness of SIMD machine algorithms, i.e., analyzing the simultaneous flow of N data items among N processors. Processor address masks, a concise notation for activating and deactivating processors, are used in the algorithms. The methods used to prove the lower bounds and to construct (and prove correct) simulation algorithms to show the upper bounds can be generalized and applied to the analysis of other networks.