Computer Interconnection Structures: Taxonomy, Characteristics, and Examples
ACM Computing Surveys (CSUR)
Ethernet: distributed packet switching for local computer networks
Communications of the ACM
Experimental Polyprocessor System (EPOS)—architecture
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Efficient message routing in Mega-Micro-Computer networks
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Hierarchical multiprocessor organizations
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Design Considerations for Single-Chip Computers of the Future
IEEE Transactions on Computers
Notes on Shuffle/Exchange-Type Switching Networks
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
IEEE Transactions on Computers
Generalized Connection Networks for Parallel Processor Intercommunication
IEEE Transactions on Computers
The cube-connected-cycles: A versatile network for parallel computation
SFCS '79 Proceedings of the 20th Annual Symposium on Foundations of Computer Science
NODAS: the network-oriented data acquisition system for the medical environment
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Interconnection networks: a survey and assessment
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
Evaluation of On-Chip Static Interconnection Networks
IEEE Transactions on Computers
Stencils and problem partitionings: their influence on the performance of multiple processor systems
IEEE Transactions on Computers
Traffic-Specific Interconnection Networks for Multicomputers
IEEE Transactions on Computers
The HCN: a versatile interconnection network based on cubes
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Flexible oblivious router architecture
IBM Journal of Research and Development
Multidimensional Network Performance with Unidirectional Links
ICPP '97 Proceedings of the international Conference on Parallel Processing
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Cost-Performance Bounds for Multimicrocomputer Networks
IEEE Transactions on Computers
Generalized Hypercube and Hyperbus Structures for a Computer Network
IEEE Transactions on Computers
On the Load Balancing Bus Accessing Scheme
IEEE Transactions on Computers
The Performance of Multimicrocomputer Networks Supporting Dynamic Workloads
IEEE Transactions on Computers
RTOIN: a new scalable optical interconnection network
Proceedings of the 2nd international conference on Scalable information systems
Fault-tolerant mapping of a mesh network in a flexible hypercube
WSEAS Transactions on Computers
Fault-tolerant meshes and tori embedded in a faulty supercube
WSEAS Transactions on Computers
Modeling the effects of hot-spot traffic load on the performance of wormhole-switched hypermeshes
Computers and Electrical Engineering
WSEAS Transactions on Information Science and Applications
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Architectures for metropolitan area networks
Computer Communications
Research note: Analysis of 1-ROR networks
Computer Communications
Graph theoretic characterization and reliability of the multiple-clique network
Mathematical and Computer Modelling: An International Journal
The number of spanning trees of the generalized hypercube network
Mathematical and Computer Modelling: An International Journal
Mathematical and Computer Modelling: An International Journal
| Hi-index | 15.00 |
This paper compares nine network interconnection schemes and introduces "dual-bus hypercubes," a cost-effective method of connecting thousands of dual-port single-chip microcomputers into a room-sized information processing system, a "network computer." Each network node is a chip containing memory and a pair of processors for tasks and input/output. Nodes are linked by shared communication buses, each conceptually spanning a D-dimensional, W-wide hypercube of N = WD nodes. Each node shares two buses. Each bus is shared by up to W nodes. The number of bus connections per node is fixed to satisfy chip pin limitations.