Computer Interconnection Structures: Taxonomy, Characteristics, and Examples
ACM Computing Surveys (CSUR)
Introduction to VLSI Systems
A layout strategy for VLSI which is provably good (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
A complexity theory for VLSI
Algorithms for vlsi networks of processors
Algorithms for vlsi networks of processors
The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI
IEEE Transactions on Computers
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
IEEE Transactions on Computers
The H Diagram: A Graphical Approach to Logic Design
IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
IEEE Transactions on Computers
A Survey of Interconnection Networks
Computer
The cube-connected-cycles: A versatile network for parallel computation
SFCS '79 Proceedings of the 20th Annual Symposium on Foundations of Computer Science
Interconnection networks: a survey and assessment
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
An Efficient Task Allocation Scheme for 2D Mesh Architectures
IEEE Transactions on Parallel and Distributed Systems
A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers
IEEE Transactions on Computers
Optimal Routing Algorithm and the Diameter of the Cube-Connected Cycles
IEEE Transactions on Parallel and Distributed Systems
Largest-job-first-scan-all scheduling policy for 2D mesh-connected systems
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Finding Maximal Submeshes in Faulty 2D Mesh in the Presence of Failed Nodes
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
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This correspondence evaluates three types of static interconnection networks for VLSI implementation. The criteria of evaluation have been selected from three orthogonal aspects-physical (chip area and dissipation), computational speed (message delay and message density) and cost (chip yield, operational reliability and layout cost). The main feature of this paper is to augment the selection criteria for the interconnection networks from the classical AT2 metric and to provide results pertaining to realistic VLSI implementation.