Introduction to VLSI Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
How to assemble tree machines (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
New layouts for the shuffle-exchange graph(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Bounds on minimax edge length for complete binary trees
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
On non-linear lower bounds in computational complexity
STOC '75 Proceedings of seventh annual ACM symposium on Theory of computing
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
A complexity theory for VLSI
Area-efficient vlsi computation
Area-efficient vlsi computation
Evaluation of On-Chip Static Interconnection Networks
IEEE Transactions on Computers
A Fast Distributed Shortest Path Algorithm for a Class of Hierarchically Clustered Data Networks
IEEE Transactions on Computers
How to assemble tree machines (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
An area-maximum edge length tradeoff for VLSI layout
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Hierarchical memory with block transfer
SFCS '87 Proceedings of the 28th Annual Symposium on Foundations of Computer Science
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In this paper, we introduce a new framework within which to study VLSI layout problems. The framework is based on a straightforward generalization of the Lipton-Tarjan notion of a planar separator and, unlike previous approaches, leads to universally close upper and lower bounds on the layout area and crossing number of an arbitrary network. In addition, the framework permits simple proofs of results previously thought to be difficult and is suitable for use with good bisection width heurisitcs.