A layout strategy for VLSI which is provably good (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Bounds on minimax edge length for complete binary trees
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Processor networks and interconnection networks without long wires
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Processor networks and interconnection networks without long wires (extended abstract)
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
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We construct an N-node graph G which has (i) a layout with area O(N) and maximum edge length O(N1/2), (ii) a layout with area O(N5/4) and maximum edge length O(N1/4). We prove for 1 ≤ f(N) ≤ O(N1/8) that any layout for G with area Nf(N) has an edge of length &Ohgr;(N1/2/f (N) •log N). Hence G has no layout which is optimal with respect to both measures.