An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Some simplified NP-complete problems
STOC '74 Proceedings of the sixth annual ACM symposium on Theory of computing
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
A complexity theory for VLSI
Theory of Self-Reproducing Automata
Theory of Self-Reproducing Automata
The VLSI Complexity of Selected Graph Problems
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
A model of computation for VLSI with related complexity results
Journal of the ACM (JACM)
On driving many long wires in a VLSI layout
Journal of the ACM (JACM)
Aspects of information flow in VLSI circuits
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
Group Properties of Cellular Automata and VLSI Applications
IEEE Transactions on Computers
Dual Systolic Architectures for VLSI Digital Signal Processing Systems
IEEE Transactions on Computers
A VLSI Solution to the Vertical Segment Visibility Problem
IEEE Transactions on Computers
Lower bounds on communication complexity in distributed computer networks
Journal of the ACM (JACM)
The Cubical Ring Connected Cycles: A Fault Tolerant Parallel Computation Network
IEEE Transactions on Computers
IEEE Transactions on Computers
Optimal VLSI circuits for sorting
Journal of the ACM (JACM)
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
On the communication complexity of graph properties
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
Energy consumption in VLSI circuits
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
The communication complexity of several problems in matrix computation
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Processor networks and interconnection networks without long wires
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Optimal VLSI architectures for multidimensional DFT
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Reconfigurable Multipipelines for Vector Supercomputers
IEEE Transactions on Computers
AT/sup 2/-Optimal Galois Field Multiplier for VLSI
IEEE Transactions on Computers
Processor networks and interconnection networks without long wires (extended abstract)
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Optimal VLSI architectures for multidimensional DFT (preliminary version)
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Optimal bounded-degree VLSI networks for sorting in a constant number of rounds
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Parallel Architectures and Algorithms for Image Component Labeling
IEEE Transactions on Pattern Analysis and Machine Intelligence
A New Class of Optimal Bounded-Degree VLSI Sorting Networks
IEEE Transactions on Computers
Storage-Efficient, Deadlock-Free Packet Routing Algorithms for Torus Networks
IEEE Transactions on Computers
A coding theorem for distributed computation
STOC '94 Proceedings of the twenty-sixth annual ACM symposium on Theory of computing
Optimal Layouts of Midimew Networks
IEEE Transactions on Parallel and Distributed Systems
Strategic directions in research in theory of computing
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1997 international symposium on Physical design
The Case for Chaotic Adaptive Routing
IEEE Transactions on Computers
Layout of the batcher bitonic sorter (extended abstract)
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Compact grid layouts of multi-level networks
STOC '99 Proceedings of the thirty-first annual ACM symposium on Theory of computing
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
The Compilation of Regular Expressions into Integrated Circuits
Journal of the ACM (JACM)
Three-Dimensional VLSI: a case study
Journal of the ACM (JACM)
Cost Trade-offs in Graph Embeddings, with Applications
Journal of the ACM (JACM)
Information Transfer in Distributed Computing with Applications to VLSI
Journal of the ACM (JACM)
Balance in architectural design
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Array processor with multiple broadcasting
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Performance-Based Constraints for Multidimensional Networks
IEEE Transactions on Parallel and Distributed Systems
Tighter Layouts of the Cube-Connected Cycles
IEEE Transactions on Parallel and Distributed Systems
VLSI layout and packaging of butterfly networks
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
Compact, multilayer layout for butterfly fat-tree
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
A VLSI layout for a pipelined Dadda multiplier
ACM Transactions on Computer Systems (TOCS)
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Solving Fundamental Problems on Sparse-Meshes
IEEE Transactions on Parallel and Distributed Systems
Information transfer and area-time tradeoffs for VLSI multiplication
Communications of the ACM
Rent's rule based switching requirements
Proceedings of the 2001 international workshop on System-level interconnect prediction
Communication complexity method for measuring nondeterminism in finite automata
Information and Computation
Layout area of the hypercube: (extended abstract)
SODA '02 Proceedings of the thirteenth annual ACM-SIAM symposium on Discrete algorithms
AT2L2 o N2/2 for fast fourier transform in multilayer VLSI
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
A survey of graph layout problems
ACM Computing Surveys (CSUR)
On the area of hypercube layouts
Information Processing Letters
IEEE Transactions on Computers
Diagonal and Toroidal Mesh Networks
IEEE Transactions on Computers
Embedding Cube-Connected Cycles Graphs into Faulty Hypercubes
IEEE Transactions on Computers
A Period-Processor-Time-Minimal Schedule for Cubical Mesh Algorithms
IEEE Transactions on Parallel and Distributed Systems
Optimal VLSI Networks for Multidimensional Transforms
IEEE Transactions on Parallel and Distributed Systems
Integration, the VLSI Journal
Cellular automata: energy consumption and physical feasibility
Fundamenta Informaticae - Special issue on cellular automata
Multidimensional Network Performance with Unidirectional Links
ICPP '97 Proceedings of the international Conference on Parallel Processing
A Direct Block-Five-Diagonal System Solver for the VLSI Parallel Model
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Randomized Communication Protocols (A Survey)
SAGA '01 Proceedings of the International Symposium on Stochastic Algorithms: Foundations and Applications
Fractional Lengths and Crossing Numbers
GD '02 Revised Papers from the 10th International Symposium on Graph Drawing
Heuristics and Experimental Design for Bigraph Crossing Number Minimization
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
Journal of Automata, Languages and Combinatorics - Third international workshop on descriptional complexity of automata, grammars and related structures
A layout strategy for VLSI which is provably good (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
The entropic limitations on VLSI computations(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
The chip complexity of binary arithmetic
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
The node cost measure for embedding graphs on the planar grid (Extended Abstract)
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
An algorithm for parallel computation of partial sums
CSC '84 Proceedings of the ACM 12th annual computer science conference on SIGCSE symposium
The importance of being square
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Tight bounds on the complexity of parallel sorting
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Lower bounds on communication complexity
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
An area-maximum edge length tradeoff for VLSI layout
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
On notions of information transfer in VLSI circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
The Shuffle-Ring: Overcoming the Increasing Degree of Hypercube
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Multilayer VLSI Layout for Interconnection Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization
Journal of Experimental Algorithmics (JEA)
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Arbitrary long digit integer sorter HW/SW co-design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Mesh-Connected Area-Time Optimal VLSI Multiplier of Large Integers
IEEE Transactions on Computers
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks
IEEE Transactions on Computers
A Combinatorial Limit to the Computing Power of VLSI Circuits
IEEE Transactions on Computers
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
Area Time Optimal VLSI Circuits for Convolution
IEEE Transactions on Computers
Two VLSI Structures for the Discrete Fourier Transform
IEEE Transactions on Computers
On Embedding Rectangular Grids in Square Grids
IEEE Transactions on Computers
Pin Limitations and Partitioning of VLSI Interconnection Networks
IEEE Transactions on Computers
A Layout for the Shuffle-Exchange Network with O(N2/log3/2N) Area
IEEE Transactions on Computers
The unpredictable deviousness of models
Theoretical Computer Science
Improving the average delay of sorting
Theoretical Computer Science
Power scalability in a mesh-connected reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS)
VLSI systolic arrays for band matrix multiplication
Integration, the VLSI Journal
Improving the average delay of sorting
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
A Systolic Design for Connectivity Problems
IEEE Transactions on Computers
Universality considerations in VLSI circuits
IEEE Transactions on Computers
Energy-Privacy trade-offs in VLSI computations
INDOCRYPT'05 Proceedings of the 6th international conference on Cryptology in India
Layout volumes of the hypercube
GD'04 Proceedings of the 12th international conference on Graph Drawing
Parceling the butterfly and the batcher sorting network
Theoretical Computer Science
On approximating the maximum simple sharing problem
ISAAC'06 Proceedings of the 17th international conference on Algorithms and Computation
Cellular Automata: Energy Consumption and Physical Feasibility
Fundamenta Informaticae - Cellular Automata
New area-time lower bounds for the multidimensional DFT
CATS 2011 Proceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 119
| Hi-index | 0.11 |
The complexity of the Discrete Fourier Transform (DFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points (N) in the DFT: AT2≥ N2/16. This inequality holds for any chip design based on any algorithm, and is nearly tight when T &equil; &thgr;(N1/2) or T &equil; &thgr;(log N). A more general lower bound is also derived: ATx &equil; &Ohgr;(N1+x/2), for 0≤×≤2.