Energy consumption in VLSI circuits

  • Authors:

  • Alok Aggarwal;Ashok Chandra;Prabhakar Raghavan

  • Affiliations:

  • IBM Research Division, Thomas J. Watson Center, P. O. Box 218, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Center, P. O. Box 218, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Center, P. O. Box 218, Yorktown Heights, New York

  • Venue:
  • STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
  • Year:
  • 1988

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Abstract

We study energy consumption in CMOS-style VLSI circuits, where a wire of length / consumes energy &THgr;(l)when switching. Three model are considered: the uniswitch model where a wire is assumed to switch at most once if the input changes, the multiswitch model which allows the possibility of multiple switches caused by uncontrolled delays, and the clock model which also takes clock distribution energy into account. Previous lower bound results for the uniswitch model applied only to circuits where intermediate data were not encoded (for example, in unary) by using additional wires and area to reduce the energy. We show that such encodings can be useful for adding two n-bit numbers using synchronous Boolean circuits (energy reduction from &THgr;(n log n) to &Ogr;(n log n/(log log n)), but not for transitive functions such as the cyclic shift of n bits (energy &THgr;(n2)). For the multiswitch model, we develop layouts that achieve energy close to the uniswitch case for these problems, and show a separation result between the uniswitch and multiswitch models. Finally, some energy-period tradeoffs are shown for the clock model.