On the Time Required to Perform Addition
Journal of the ACM (JACM)
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
Information transfer and area-time tradeoffs for VLSI multiplication
Communications of the ACM
The Complexity of Computing
Introduction to VLSI Systems
Structure of Computers and Computations
Structure of Computers and Computations
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
The VLSI Complexity of Selected Graph Problems
Journal of the ACM (JACM)
A model of computation for VLSI with related complexity results
Journal of the ACM (JACM)
On driving many long wires in a VLSI layout
Journal of the ACM (JACM)
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs
IEEE Transactions on Computers
Energy consumption in VLSI circuits
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
Scans as Primitive Parallel Operations
IEEE Transactions on Computers
A recursive algorithm for binary multiplication and its implementation
ACM Transactions on Computer Systems (TOCS)
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
The Compilation of Regular Expressions into Integrated Circuits
Journal of the ACM (JACM)
Information Transfer in Distributed Computing with Applications to VLSI
Journal of the ACM (JACM)
A VLSI layout for a pipelined Dadda multiplier
ACM Transactions on Computer Systems (TOCS)
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
The entropic limitations on VLSI computations(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
A Combinatorial Limit to the Computing Power of VLSI Circuits
IEEE Transactions on Computers
Area-Time Optimal Fast Implementation of Several Functions in a VLSI Model
IEEE Transactions on Computers
Much ado about two (pearl): a pearl on parallel prefix computation
Proceedings of the 35th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An architecture for a VLSI FFT processor
Integration, the VLSI Journal
An area-time efficient NMOS adder
Integration, the VLSI Journal
RTRAM: reconfigurable and testable multi-bit RAM design
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Residue-weighted number conversion using signed-digit number for moduli set {22n - 1, 22n+1 - 1, 2n}
Analog Integrated Circuits and Signal Processing
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The chip complexity of a computation is concerned with the chip area, A, and the time, T, required to perform the computation when implemented on a chip. An area-time product AT&agr;,for &agr; ≥ 0, is used as a complexity measure. A particular value of &agr;, which is chosen by the user, reflects the relative importance between A and T. This paper derives lower and upper bounds on the area-time complexity for chips that implement binary arithmetic, assuming a model of computation which is intended to approximate, current and anticipated LSI or VLSI technology.