Bounds on minimax edge length for complete binary trees
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
The chip complexity of binary arithmetic
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
Testing and diagnosis of interconnects using boundary scan architecture
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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It is assumed that long wires represent large capacitive loads, and the effect on the area of a VLSI layout when drivers are introduced along many long wires in the layout is investigated. A layout is presented for which the introduction of standard drivers along long wires squares the area of the layout; it is shown, however, that the increase in area is never greater than the layout's area squared if the driver can be laid out in a square region. This paper also shows an area-time trade-off for the driver of a single long wire of length / by which the area of the driver from &THgr;(l), to &THgr;(lq), q ll-q) rather than &THgr;(log l) can be tolerated. Tight bounds are also obtained on the worst-case area increase in general layouts having these drivers.