Introduction to VLSI Systems
Parallel algorithms for data compression
Journal of the ACM (JACM)
On driving many long wires in a VLSI layout
Journal of the ACM (JACM)
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers
Tradeoffs for VLSI models with subpolynomial delay
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Efficient embeddings of binary trees in VLSI arrays
IEEE Transactions on Computers
On Implementing Large Binary Tree Architectures in VLSI and WSI
IEEE Transactions on Computers
An Upper Bound on Expected Clock Skew in Synchronous Systems
IEEE Transactions on Computers
Placement of the Processors of a Hypercube
IEEE Transactions on Computers
Optimal Layouts of Midimew Networks
IEEE Transactions on Parallel and Distributed Systems
Work-preserving emulations of fixed-connection networks
Journal of the ACM (JACM)
Three-Dimensional VLSI: a case study
Journal of the ACM (JACM)
IEEE Transactions on Computers
Synchronizing large VLSI processor arrays
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
How to assemble tree machines (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
A layout strategy for VLSI which is provably good (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Dictionary machines with a small number of processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An area-maximum edge length tradeoff for VLSI layout
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Expansion of layouts of complete binary trees into grids
Discrete Applied Mathematics
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Information is not transferred instantaneously; there is always a propagation delay before an output is available as an input to the next computational step. Propagation delay is a function of wire length, so we study the length of edges in planar graphs. We prove matching (to within a constant factor) upper and lower bounds on minimax edge length for four planar embedding problems for complete binary trees. (The results are summarized in Table 1.) Because trees are often subcircuits of larger circuits, these results imply general performance limits due to propagation delay. The results give important information for the popular technique of pipelining.