An area-maximum edge length trade-off for VSLI layout
Information and Control - The MIT Press scientific computation series
Restructuring hexagonal arrays of processors in the presence of faults
Advances in VLSI and Computer Systems
Area-Efficient VLSI Computation
Area-Efficient VLSI Computation
Introduction to VLSI Systems
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
How to assemble tree machines (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Bounds on minimax edge length for complete binary trees
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Design considerations for the VLSI processor of X-TREE
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Computational Aspects of VLSI
The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI
IEEE Transactions on Computers
Wafer-Scale Integration of Systolic Arrays
IEEE Transactions on Computers
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
IEEE Transactions on Computers
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
IEEE Transactions on Computers
Embedding Tree Structures in VLSI Hexagonal Arrays
IEEE Transactions on Computers
On Implementing Large Binary Tree Architectures in VLSI and WSI
IEEE Transactions on Computers
VLSI layout of trees into grids of minimum width
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
A Robust Parallel Architecture for Adaptive Color Quantization
ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
Expansion of layouts of complete binary trees into grids
Discrete Applied Mathematics
Minimum congestion embedding of complete binary trees into tori
COCOON'99 Proceedings of the 5th annual international conference on Computing and combinatorics
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We consider the problem of embedding a complete binary tree in squareor hexagonally-connected VLSI arrays Of processing elements (PE's). This problem can be solved in a radically different manner from current layout techniques which are aimed at laying out a given graph in the plane. The difference is due to the fact that a PE can be used both as a tree node and as a connecting element between distant nodes. New embedding schemes are presented in which (asymptotically) 100 percent of the PE's are utilized as tree nodes. This is a significant savings over known schemes, which achieve 50 percent utilization (the well-known H-tree) and 71 percent for some hexagonal schemes. These schemes also speed up signal propagation from the root to the leaves.