Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
Efficient embeddings of binary trees in VLSI arrays
IEEE Transactions on Computers
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Channel-Constrained Reconfiguration Approach for Processing Arrays
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Characterization, testing and reconfiguration of faults in mesh networks
Integration, the VLSI Journal
Information Processing Letters
On the reconfiguration algorithm for fault-tolerant VLSI arrays
ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Loop based design for wafer scale systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On fault tolerance of two-dimensional mesh networks
ICDCN'06 Proceedings of the 8th international conference on Distributed Computing and Networking
An integrated highly parallel architecture for image reconstruction
EGGH'88 Proceedings of the Third Eurographics conference on Advances in Computer Graphics Hardware
| Hi-index | 14.99 |
VLSI technologists are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating "around" such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NP-complete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of the work to problems in VLSI layout theory, graph theory, fault-tolerant systems, planar geometry, and the probabilistic analysis of algorithms.