A fault tolerant massively parallel processing architecture
Journal of Parallel and Distributed Computing
Introduction to algorithms
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
Integration, the VLSI Journal
Counting the number of fault patterns in redundant VLSI arrays
Information Processing Letters
On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
Integration, the VLSI Journal
Catastrophic faults in reconfigurable systolic linear arrays
Discrete Applied Mathematics
Testing and reconfiguration of VLSI linear arrays
Theoretical Computer Science
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
DAP—a distributed array processor
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
On characterization of catastrophic faults in two-dimensional VLSI arrays
Integration, the VLSI Journal
Wafer-Scale Integration of Systolic Arrays
IEEE Transactions on Computers
Design of a Massively Parallel Processor
IEEE Transactions on Computers
Computer
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Achieving fault-tolerance through incorporation of redundancy and reconfiguration is quite common. The distribution of faults can have several impacts on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire VLSI system unusable regardless of its component redundancy and its reconfiguration capabilities. Such fault patterns are called catastrophic fault patterns (CFPs). In this paper, we characterize catastrophic fault patterns in mesh networks when the links are bidirectional or unidirectional. We determine the minimum number of faults required for a fault pattern to be catastrophic. We consider the problem of testing whether a fault pattern is catastrophic. When a fault pattern is not catastrophic we study the problem of finding optimal reconfiguration strategies, where optimality is with respect to either the number of processing elements in the reconfigured network (the reconfiguration is optimal if such a number is maximized) or the number of bypass links to activate in order to reconfigure the array (the reconfiguration is optimal if such a number is minimized). The problem of finding a reconfiguration strategy that is optimal with respect to the size of the reconfigured network is NP-complete, when the links are bidirectional, while it can be solved in polynomial time, when the links are unidirectional. Considering optimality with respect to the number of bypass links to activate, we provide algorithms which efficiently find an optimal reconfiguration.