Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A multiprocessor architecture for two-dimensional digital filters
IEEE Transactions on Computers
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
Unique design concepts on GF11 and their impact on performance
IBM Journal of Research and Development
Implementation of a SliM Array Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
ManArray Processor Interconnection Network: An Introduction
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Thirty Years of Parallel Image Processing
VECPAR '00 Selected Papers and Invited Talks from the 4th International Conference on Vector and Parallel Processing
A Linear Array Parallel Image Processor: SliM-II
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Data broadcasting in linearly scheduled array processors
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The impact of grain size on the efficiency of embedded SIMD image processing architectures
Journal of Parallel and Distributed Computing
One long argument: Azriel Rosenfeld and the genesis of modern image systems
Pattern Recognition Letters - Special issue: In memoriam Azriel Rosenfeld
Characterization, testing and reconfiguration of faults in mesh networks
Integration, the VLSI Journal
A Comparative Performance Study of an Interconnection Cached Network
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Bit-Serial Parallel Processing Systems
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
A Robust Matrix-Multiplication Array
IEEE Transactions on Computers
A Microprocessor-Based Office Image Processing System
IEEE Transactions on Computers
A Variable-Length Shift-Register
IEEE Transactions on Computers
Self-Diagnosing Cellular Implementations of Finite-State Machines
IEEE Transactions on Computers
Parallel processing for image and video processing: Issues and challenges
Parallel Computing
Application of the massively parallel processor to database management systems
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
Universities and the future of high-performance computing technology
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
Challenges of massive parallelism
IJCAI'93 Proceedings of the 13th international joint conference on Artifical intelligence - Volume 1
Massively parallel artificial intelligence
IJCAI'91 Proceedings of the 12th international joint conference on Artificial intelligence - Volume 1
APRON: a cellular processor array simulation and hardware design tool
EURASIP Journal on Advances in Signal Processing - CNN technology for spatiotemporal signal processing
Artificial Intelligence
Shuffling with the Illiac and PM2I SIMD Networks
IEEE Transactions on Computers
Edge detection using fine-grained parallelism in VLSI
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
Upper bounds on the connection probability for 2-D meshes and tori
Journal of Parallel and Distributed Computing
A high efficient on-chip interconnection network in SIMD CMPs
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Closed-form reliability expression of large non-homogeneous distributed system
Mathematical and Computer Modelling: An International Journal
Performance analysis in a 4096 processor environment
Journal of Systems and Software
Pattern Recognition Letters
Low-Power High-Speed Hybrid Wave-Pipeline Architectures for Binary Morphological Dilation
Journal of Signal Processing Systems
A generalised parallel architecture for image based algorithms
EGGH'89 Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware
| Hi-index | 15.01 |
The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16 384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.