Implementation of Data Manipulating Functions on the STARAN Associative Processor
Proceedings of the Sagamore Computer Conference on Parallel Processing
The universality of various types of SIMD machine interconnection networks
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
A Large Scale, Homogenous, Fully Distributed Parallel Machine, II
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
On the Augmented Data Manipulator Network in SIMD Environments
IEEE Transactions on Computers
IEEE Transactions on Computers
Destination tag routing techniques based on a state model for the LADM network
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A Fault-Tolerant Mapping Scheme for a Configurable Multiprocessor System
IEEE Transactions on Computers
The PM221 Interconnection Network
IEEE Transactions on Computers
Processor networks and interconnection networks without long wires
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
Equivalence Between Functionality and Topology of Log N-Stage Banyan Networks
IEEE Transactions on Computers
Processor networks and interconnection networks without long wires (extended abstract)
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Destination Tag Routing Techniques Based on a State Model for the IADM Network
IEEE Transactions on Computers
Fast Self-Routing Permutation Switching on an Asymptotically Minimum Cost Network
IEEE Transactions on Computers
Performance analysis of redundant-path networks for multiprocessor systems
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Computers
Topologies of Combined (2logN - 1)-Stage Interconnection Networks
IEEE Transactions on Computers
Architecture of a massively parallel processor
25 years of the international symposia on Computer architecture (selected papers)
A new approach to fast control of r2× r2 3-stage benes networks of r×r crossbar switches
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Performing Permutations on Interconnection Networks by Regularly Changing Switch States
IEEE Transactions on Parallel and Distributed Systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
The shuffle/exchange-plus networks
ACM-SE 20 Proceedings of the 20th annual Southeast regional conference
IEEE Transactions on Computers
Creating Disjoint Paths in Gamma Interconnection Networks
IEEE Transactions on Computers
Orthogonal Graphs for the Construction of a Class of Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Functional and Topological Relations Among Banyan Multistage Networks of Differing Switch Sizes
IEEE Transactions on Parallel and Distributed Systems
Reconfiguration with Time Division Multiplexed MIN's for Multiprocessor Communications
IEEE Transactions on Parallel and Distributed Systems
Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A control processor for a reconfigurable array computer
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Probabilistic analysis of a crossbar switch
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Dynamic rerouting tag schemes for the augmented data manipulator network
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
MIMD machine communication using the augmented data manipulator network
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Fault tolerance of a class of connecting networks
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Architecture of a massively parallel processor
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
An emulator network for SIMD machine interconnection networks
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Siamese-Twin: A Dynamically Fault-Tolerant Fat-Tree
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
A New Tag Scheme and Its Tree Representation for a Shuffle-Exchange Network
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A Combinatorial Problem Concerning Processor Interconnection Networks
IEEE Transactions on Computers
Parallel Processing Approaches to Image Correlation
IEEE Transactions on Computers
Analysis and Simulation of Buffered Delta Networks
IEEE Transactions on Computers
On the Number of Permutations Performable by the Augmented Data Manipulator Network
IEEE Transactions on Computers
Bit-Serial Parallel Processing Systems
IEEE Transactions on Computers
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
IEEE Transactions on Computers
The Universality of the Shuffle-Exchange Network
IEEE Transactions on Computers
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
The Reverse-Exchange Interconnection Network
IEEE Transactions on Computers
Design of a Massively Parallel Processor
IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Routing Schemes for the Augmented Data Manipulator Network in an MIMD System
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
Performance and reliability analysis of new fault-tolerant advance omega network
WSEAS Transactions on Computers
MPP: a supersystem for satellite image processing
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
A new min: fault-tolerant advance omega network
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.08 |
Four SIMD multistage networks - Feng's data manipulator, STARAN flip network, omega network, and indirect binary n-cube—are analyzed. Three parameters - topology, interchange box, and control structure—are defined. It is shown that the latter three networks use equivalent topologies and differences in their capabilities result from the other parameters. An augmented data manipulator network using a modified control structure to perform more single pass interconnections than the other networks is presented. Some problems may be solved more efficiently if the 2n processing elements of an SIMD machine can be partitioned into submachines of size 2r. Single and multiple control partitioning are defined. The capabilities of these multistage networks to perform in these partioned environments are discussed.