Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
A microprocessor-controlled asynchronous circuit switching network
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Poly-Processor System analysis and design
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Graphs and Hypergraphs
Realizing Fault-Tolerant Interconnection Networks Via Chaining
IEEE Transactions on Computers - Fault-Tolerant Computing
Failure Dependent Bandwidth in Shuffle-Exchange Networks
IEEE Transactions on Computers
Design and Analysis of Dynamic Redundancy Networks
IEEE Transactions on Computers
A fault-tolerant scheme for multistage interconnection networks
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Design of a 2 × 2 fault-tolerant switching element
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
IBM Journal of Research and Development
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Several proposals have been made for using a class of connecting networks called &bgr;-networks in multicomputer systems, such as systems containing large numbers of microprocessors. A &bgr;-network is a network of 2 × 2 crossbar switches called &bgr;-elements. This paper presents an analysis of the fault tolerance of &bgr;-networks intended for multicomputer applications. A fault model is used which allows &bgr;-elements to be stuck in either of their two normal states. A new connectivity property called dynamic full access (DFA) is introduced which serves as the criterion for fault tolerance. A &bgr;-network is said to have the DFA property if each of its inputs can be connected to any of its outputs in a finite number of passes through the network. A fault is called critical if it destroys the DFA property. Two graph-theoretical characterizations of the critical faults of a &bgr;-network are presented. It is shown that there is a one-to-one correspondence between minimal critical faults and the cutsets of the circuit adjacency graphs derived from the &bgr;-network. It is further shown that a fault is critical if and only if it is incompatible with all Eulerian circuits associated with the &bgr;-network. Some applications of the theory are discussed.