Fault tolerance of a class of connecting networks
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Modeling of a Bubble-Memory Organization with Self-Checking Translators to Achieve High Reliability
IEEE Transactions on Computers
Technology and Design Tradeoffs in the Creation of a Modern Supercomputer
IEEE Transactions on Computers
Implementation of an Experimental Fault-Tolerant Memory System
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A Survey of Interconnection Networks
Computer
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This paper describes a coding scheme developed for a specific supercomputer architecture and structure. The code considered is a shortened (b,k)-adjacent single-error-correcting double-error probabilistic-detecting code with b = 5, k = 1, and code group width = 4. An evaluation of the probabilistic double-error-detection capability of the code was performed for drfferent organizations of the coding/decoding strategies for the codewords. This led to the selection of a system organization encompassing the traditional feature of memory data error protection and also providing for the detection of major addressing errors that may result from faults affecting the interconnection network communication modules. The cost of implementation is a limited amount of extra hardware and a negligible degradation in the double-error-detection properties of the code.