Poly-Processor System analysis and design

Authors:
K. Hurakami;S. Nishikawa;M. Sato
Affiliations:
Musashino Electrical Communication laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, 180, Japan;Musashino Electrical Communication laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, 180, Japan;Musashino Electrical Communication laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, 180, Japan
Venue:
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Year:
1977

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Abstract

This paper discusses the structure and efficiency of a computer complex constructed of many small, tightly coupled, functionally dedicated processors called a Poly-Processor System (PPS). The objective of the PPS is to realize a computer system which has easier expandability, higher reliability and better cost-to-performance ratio than existing systems. Firstly, presented are rules to assign functions among processors, memories and interconnection modules. Secondly, dynamic behavior of the system, such as the frequency of interprocesser communication and instruction occurance, is analyzed by computer simulation. Lastly, a pilot model (PPS for Research: PPS-R), developed to confirm the feasibility of the system and to acquire experience in establishing the architecture of the system, is described.