Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
On the Number of Permutations Performable by the Augmented Data Manipulator Network
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
IEEE Transactions on Computers
An overview of the Texas reconfigurable array computer
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
Determining an Optimal Secondary Storage Service Rate for the PASM Control System
IEEE Transactions on Computers
Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks
IEEE Transactions on Computers - The MIT Press scientific computation series
A connecting network with fault tolerance capabilities
IEEE Transactions on Computers - The MIT Press scientific computation series
Flexible oblivious router architecture
IBM Journal of Research and Development
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Data Exchange Optimization in Reconfigurable
IEEE Transactions on Computers
Task Preloading Schemes for Reconfigurable Parallel Processing Systems
IEEE Transactions on Computers
Efficient Internode Communications in Reconfigurable Binary Trees
IEEE Transactions on Computers
Shuffling with the Illiac and PM2I SIMD Networks
IEEE Transactions on Computers
Modified composite Banyan network with an enhanced terminal reliability
Computer Communications
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There have been many multistage interconnection networks proposed in the literature for interconnecting the processors that comprise large parallel processing systems. In this paper, the use of the Augmented Data Manipulator and Inverse Augmented Data Manipulator multistage networks in the MIMD mode of operation is considered. A tag based routing scheme which allows distributed control of either network is proposed. Rerouting schemes that allow a message blocked by a busy or known faulty node in its present path to dynamically make use of a nonbusy node and continue, when possible, are described for both networks. Finally, a tag based broadcasting scheme for the networks is introduced that allows one processor to send messages to a subset of the other processors.