The Indirect Binary n-Cube Microprocessor Array

Authors:
M. C. , III Pease
Affiliations:
Information Science Laboratory of the. Information Science and Engineering Division, Stanford Research Institute
Venue:
IEEE Transactions on Computers
Year:
1977

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Abstract

This paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism. By microprocessor we mean a processor realized on one or a few semiconductor chips that include arithmetic and logical facilities and some memory. The current state of LSI technology makes this approach a feasible and attractive candidate for use in a macrocomputer facility.