Designing a high performance and fault tolerant multistage interconnection network with easy dynamic rerouting

Authors:
Ching-Wen Chen;Phui-Si Gan;Chih-Hung Chang
Affiliations:
Department of Computer Science and Information Engineering, Chaoyang University of Technology, Wufeng, Taichung County, Taiwan, ROC;Department of Computer Science and Information Engineering, Chaoyang University of Technology, Wufeng, Taichung County, Taiwan, ROC;Department of Computer Science and Information Engineering, Chaoyang University of Technology, Wufeng, Taichung County, Taiwan, ROC
Venue:
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
Year:
2004

Citing 11
Cited 0

A Survey and Comparision of Fault-Tolerant Multistage Interconnection Networks

Computer
The Extra Stage Gamma Network

IEEE Transactions on Computers
The B-Network: A Multistage Interconnection Network with Backward Links

IEEE Transactions on Computers
CGIN: A Fault Tolerant Modified Gamma Interconnection Network

IEEE Transactions on Parallel and Distributed Systems
The Composite Banyan Network

IEEE Transactions on Parallel and Distributed Systems
Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network

ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
The Gamma Network

IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array

IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks

IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor

IEEE Transactions on Computers
A Survey of Interconnection Networks

Computer

Quantified Score

Hi-index	0.00

Visualization

Abstract

Designing a reliable and high performance multistage interconnection network (MIN) should consider the following issues carefully: (1) fault tolerance guarantee; (2) easy schemes and hardware design of rerouting switches; (3) low rerouting resulting in a low collision ratio. In this paper, we present the High Performance Chained Multistage Interconnection Network (HPCMIN) which has one-fault tolerance, destination tag routing for easy rerouting, one rerouting hop, resulting in a low collision ratio. From our simulation results, the HPCMIN results in a lower collision ratio than other dynamic rerouting networks. The HPCMIN is embedded with the indirect binary n-cube network(the ICube network) which is equivalent to many important MINs. Thus, the design methods used in the HPCMIN can be applied to these MINs so that they have the characteristics of the HPCMIN.