Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Multiprocessor systems: interconnection networks, memory hierarchy, modeling and simulations
Multiprocessor systems: interconnection networks, memory hierarchy, modeling and simulations
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
The NYU Ultracomputer Designing an MIMD Shared Memory Parallel Computer
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Performance of unbuffered shuffle-exchange networks
IEEE Transactions on Computers - The MIT Press scientific computation series
The average complexity of depth-first search with backtracking and cutoff
IBM Journal of Research and Development
On the permutation capability of multistage interconnection networks
IEEE Transactions on Computers
Stencils and problem partitionings: their influence on the performance of multiple processor systems
IEEE Transactions on Computers
Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
IEEE Transactions on Computers
Traffic-Specific Interconnection Networks for Multicomputers
IEEE Transactions on Computers
Traffic studies of unbuffered Delta networks
IBM Journal of Research and Development
Multidimensional Network Performance with Unidirectional Links
ICPP '97 Proceedings of the international Conference on Parallel Processing
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A Customizable Simulator for Workstation Networks
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Performing BMMC Permutations in Two Passes through the Expanded Delta Network and MasPar MP-2
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Performance Analysis of Optical Multistage Interconnection Networks with Limited Crosstalk
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 15 - Volume 16
A collision model for randomized routing in fat-tree networks
Journal of Parallel and Distributed Computing
Multistage Interconnection Networks with Multiple Outlets
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A Comparative Performance Study of an Interconnection Cached Network
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers
IEEE Transactions on Parallel and Distributed Systems
MLMIN: A multicore processor and parallel computer network topology for multicast
Computers and Operations Research
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Proceedings of the 45th annual Design Automation Conference
A New Dimension Analysis on Blocking Behavior in Banyan-Based Optical Switching Networks
IEICE - Transactions on Information and Systems
Evolutionary optimization of multistage interconnection networks performance
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
Analysis of space-time tradeoffs in photonic switching networks
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
Packet chaining: efficient single-cycle allocation for on-chip networks
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Overview: Switching structures for ATM
Computer Communications
Interconnection network front-end controller combining to reduce hot spots effects
Computer Communications
An analytical model for the performance of buffered multicast banyan networks
Computer Communications
A high speed scheduler/controller for unbuffered banyan networks
Computer Communications
Channel reservation protocol for over-subscribed channels and destinations
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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This paper studies the performance of unbuffered and buffered, packet-switching, multistage interconnection networks. We begin by reviewing the definition of banyan networks and introducing some generalizations of them. We then present an asymptotic analysis of the performance of unbuffered banyan networks, thereby solving a problem left open by Patel. We analyze the performance of the unbuffered generalized banyan networks, and compare networks with approximately equivalent hardware complexity. Finally, we analyze the performance of buffered banyan networks and again compare networks with approximately equivalent hardware complexity.