Distributed Processor Communication Architecture
Distributed Processor Communication Architecture
Design and Analysis of Computer Communication Networks
Design and Analysis of Computer Communication Networks
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Vlsi communication components for multicomputer networks
Vlsi communication components for multicomputer networks
Lu decomposition on a multiprocessing system with communications delay
Lu decomposition on a multiprocessing system with communications delay
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
Cost-Performance Bounds for Multimicrocomputer Networks
IEEE Transactions on Computers
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
The NYU Ultracomputer Designing an MIMD Shared Memory Parallel Computer
IEEE Transactions on Computers
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
Processor Interconnection Strategies
IEEE Transactions on Computers
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
IEEE Transactions on Computers
Pin Limitations and Partitioning of VLSI Interconnection Networks
IEEE Transactions on Computers
A Perspective on Distributed Computer Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
| Hi-index | 14.98 |
Special-purpose networks of processors and intelligent switching devices can be programmed to solve problems with inherent parallelism. The target algorithm is coded into a number of asynchronously executing parallel tasks, and assigned to specific processors. For well-known algorithms, information about the data communicated between these tasks (traffic) can be characterized and used by a heuristic algorithm to produce a specialized interconnection network of switching devices at a lower cost and increased performance over the use of a general purpose structure. A program was developed which uses intertask communications to automatically generate interconnection structures of switch chips (SC's). Simulation results were used to compare cost/performance measures for the program-generated networks with some well-known structures, using both statistically generated traffic patterns and the simulation of real applications.