An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Communications of the ACM
Communications of the ACM
IEEE Transactions on Computers
AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks
IEEE Transactions on Computers
Permutations on Illiac IV-Type Networks
IEEE Transactions on Computers
Reducing the Diameters of Computer Networks
IEEE Transactions on Computers
Dual Systolic Architectures for VLSI Digital Signal Processing Systems
IEEE Transactions on Computers
Clock synchronization of a large multiprocessor system in the presence of malicious faults
IEEE Transactions on Computers
Path hierarchies in interconnection networks
IBM Journal of Research and Development
A new interconnection network for SIMD computers: the sigma networks
IEEE Transactions on Computers
Programming cellular permutation networks through decomposition of symmetric groups
IEEE Transactions on Computers
Optimal Graph Algorithms on a Fixed-Size Linear Array
IEEE Transactions on Computers
Traffic-Specific Interconnection Networks for Multicomputers
IEEE Transactions on Computers
New Connectivity and MSF Algorithms for Shuffle-Exchange Network and PRAM
IEEE Transactions on Computers
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
On an Optimally Fault-Tolerant Multiprocessor Network Architecture
IEEE Transactions on Computers
Performance analysis of the FFT algorithm on a shared-memory parallel architecture
IBM Journal of Research and Development
Best worst mappings for the omega network
IBM Journal of Research and Development
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
IEEE Transactions on Computers
A Characterization and Analysis of Parallel Processor Interconnection Networks
IEEE Transactions on Computers
Multiscattering on the cube-connected cycles
Parallel Computing
A nonblocking architecture for broadband multichannel switching
IEEE/ACM Transactions on Networking (TON)
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Optimizing Parallel Bitonic Sort
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
On the Rearrangeability of Multistage Networks Employing Uniform Connection Patterns
ADVIS '00 Proceedings of the First International Conference on Advances in Information Systems
Distributed Input and Deflection Routing Based Packet Switch Using Shuffle Pattern Network
NETWORKING '00 Proceedings of the IFIP-TC6 / European Commission International Conference on Broadband Communications, High Performance Networking, and Performance of Communication Networks
Performing BMMC Permutations in Two Passes through the Expanded Delta Network and MasPar MP-2
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
A state-of-the-art SIMD two-dimensional FFT array processor
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
The Shuffle-Ring: Overcoming the Increasing Degree of Hypercube
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Emulating Direct Products by Index-Shuffle Graphs
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
High-Performance Self-Routing Algorithm for Multiprocessor Systems with Shuffle Interconnections
IEEE Transactions on Parallel and Distributed Systems
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
Journal of Parallel and Distributed Computing
Recursive construction of parallel distribution networks
Journal of Parallel and Distributed Computing
On the Rearrangeability of Reverse Shuffle/Exchange Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
On Sorting Multiple Bitonic Sequences
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Low Diameter Interconnections for Routing in High-Performance Parallel Systems
IEEE Transactions on Computers
An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator
Integration, the VLSI Journal
Optimal Sorting Algorithms for Parallel Computers
IEEE Transactions on Computers
Parallel Algorithms to Set Up the Benes Permutation Network
IEEE Transactions on Computers
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks
IEEE Transactions on Computers
Broadcast Communications and Distributed Algorithms
IEEE Transactions on Computers
Dense Trivalent Graphs for Processor Interconnection
IEEE Transactions on Computers
IEEE Transactions on Computers
Binary Trees and Parallel Scheduling Algorithms
IEEE Transactions on Computers
Notes on Shuffle/Exchange-Type Switching Networks
IEEE Transactions on Computers
Dynamic Memories with Rapid Random and Sequential Access
IEEE Transactions on Computers
Data Manipulating Functions in Parallel Processors and Their Implementations
IEEE Transactions on Computers
Analysis and Simulation of Buffered Delta Networks
IEEE Transactions on Computers
Experience with Multiprocessor Algorithms
IEEE Transactions on Computers
IEEE Transactions on Computers
Generalized Hypercube and Hyperbus Structures for a Computer Network
IEEE Transactions on Computers
Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
IEEE Transactions on Computers
IEEE Transactions on Computers
The Prime Memory System for Array Access
IEEE Transactions on Computers
The Universality of the Shuffle-Exchange Network
IEEE Transactions on Computers
A Self-Routing Benes Network and Parallel Permutation Algorithms
IEEE Transactions on Computers
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
IEEE Transactions on Computers
Divide-and-Conquer for Parallel Processing
IEEE Transactions on Computers
Time-Space Tradeoffs on Back-to-Back FFT Algorithms
IEEE Transactions on Computers
Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations
IEEE Transactions on Computers
A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines
IEEE Transactions on Computers
The Theory Underlying the Partitioning of Permutation Networks
IEEE Transactions on Computers
The Reverse-Exchange Interconnection Network
IEEE Transactions on Computers
Implementation of Permutation Functions in Illiac IV-Type Computers
IEEE Transactions on Computers
Fast Random and Sequential Access to Dynamic Memories of Any Size
IEEE Transactions on Computers
Two VLSI Structures for the Discrete Fourier Transform
IEEE Transactions on Computers
A VLSI Network for Variable Size FFT's
IEEE Transactions on Computers
Interference Analysis of Shuffle/Exchange Networks
IEEE Transactions on Computers
The Expression Processor: A Pipelined, Multiple- Processor Architecture
IEEE Transactions on Computers
Optimality of a Two-Phase Strategy for Routing in Interconnection Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Fast Hadamard Transform Using the H Diagram
IEEE Transactions on Computers
Design of Testable Structures Defined by Simple Loops
IEEE Transactions on Computers
Packet Switching Networks for Multiprocessors and Data Flow Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Unified Matrix Treatment of the Fast Walsh-Hadamard Transform
IEEE Transactions on Computers
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Dynamic Memories with Fast Random and Sequential Access
IEEE Transactions on Computers
Hypertree: A Multiprocessor Interconnection Topology
IEEE Transactions on Computers
Self-Diagnosing Cellular Implementations of Finite-State Machines
IEEE Transactions on Computers
The Lens Interconnection Strategy
IEEE Transactions on Computers
A Layout for the Shuffle-Exchange Network with O(N2/log3/2N) Area
IEEE Transactions on Computers
Design and Performance of Generalized Interconnection Networks
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
Generalized Connection Networks for Parallel Processor Intercommunication
IEEE Transactions on Computers
Permutation algorithms on optical multi-trees
Computers & Mathematics with Applications
A versatile VLSI fast Fourier transform processor
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
Aircraft conflict detection in an associative processor
AFIPS '73 Proceedings of the June 4-8, 1973, national computer conference and exposition
STARAN parallel processor system hardware
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Interconnection networks: a survey and assessment
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
General-purpose integrated indexing circuits: a proposal
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
The architecture of MANIP: a parallel computer system for solving NP-complete problems
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Parallel sort and join for high speed database machine operations
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Numerical algorithms for parallel computers
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
Design and implementation of the banyan interconnection network in TRAC
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
A multiprocessor with replicated shared memory
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
Applications of SIMD computers in signal processing
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
Distributed scheduling of resources on interconnection networks
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
Parallel Algorithms for the Execution of Relational Database Operations Revisited On Grids
International Journal of High Performance Computing Applications
A Shuffle-Exchange Network with Simplified Control
IEEE Transactions on Computers
On rearrangeability of tandem connection of banyan-type networks
IEEE Transactions on Communications
Dynamic memories with faster random and sequential access
IBM Journal of Research and Development
An architecture for a VLSI FFT processor
Integration, the VLSI Journal
Paper: Nearest neighbor classification on two types of SIMD machines
Parallel Computing
Paper: Hybrid systolic sorters
Parallel Computing
Simulating the bitonic sort using P systems
WMC'07 Proceedings of the 8th international conference on Membrane computing
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
Shuffling with the Illiac and PM2I SIMD Networks
IEEE Transactions on Computers
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
IEEE Transactions on Computers
VLSI Sorting with Reduced Hardware
IEEE Transactions on Computers
A Comparative Study of Distributed Resource Sharing on Multiprocessors
IEEE Transactions on Computers
A Classification of Cube-Connected Networks with a Simple Control Scheme
IEEE Transactions on Computers
A systolic VLSI architecture for multi-dimensional transforms
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
IEEE Transactions on Computers - Special issue on parallel processors and processing
The multidimensional access memory in STARAN
IEEE Transactions on Computers - Special issue on parallel processors and processing
A fast parallel algorithm for routing in permutation networks
IEEE Transactions on Computers
Kronecker products and shuffle algebra
IEEE Transactions on Computers
FPGA vs. multi-core CPUs vs. GPUs: hands-on experience with a sorting application
Facing the multicore-challenge
FPGA vs. multi-core CPUs vs. GPUs: hands-on experience with a sorting application
Facing the multicore-challenge
GPU-efficient recursive filtering and summed-area tables
Proceedings of the 2011 SIGGRAPH Asia Conference
Computer generation of streaming sorting networks
Proceedings of the 49th Annual Design Automation Conference
Research: MS4 - a high performance output buffering ATM switch
Computer Communications
Topological properties of the recursive Petersen architecture
Mathematical and Computer Modelling: An International Journal
A mathematical abstraction of the rearrangeability conjecture for shuffle-exchange networks
Operations Research Letters
Parallel database sort and join operations revisited on grids
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
A sound and complete abstraction for reasoning about parallel prefix sums
Proceedings of the 41st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
Analytical performance modeling of shuffle-exchange inspired mesh-based Network-on-Chips
Performance Evaluation
A method of batching conflict routings in shuffle-exchange networks
Theoretical Computer Science
| Hi-index | 15.20 |
Given a vector of N elements, the perfect shuffle of this vector is a permutation of the elements that are identical to a perfect shuffle of a deck of cards. Elements of the first half of the vector are interlaced with elements of the second half in the perfect shuffle of the vector.