An Architecture for Bitonic Sorting with Optimal VLSI Performnance

Authors:
Gianfranco Bilardi;Franco P. Preparata
Affiliations:
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL.;Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL.
Venue:
IEEE Transactions on Computers
Year:
1984

Citing 7
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Abstract

We propose a class of designs of a new interconnection network, the pleated cube-connected cycles (PCCC), which can impleement stable bitonic sorting of n records of size q in area A = O(q2n2/T2), where T, the computation time, is in the range [驴(q log2 n), O(q 驴n/(q+ log n))]. Thus, this network is an AT2,/R-optimal bitonic sorter in the synchronous VLSI model of computation under the word-local restriction.