A VLSI Solution to the Vertical Segment Visibility Problem
IEEE Transactions on Computers
A VLSI Implementation of the Simplex Algorithm
IEEE Transactions on Computers
Optimal Graph Algorithms on a Fixed-Size Linear Array
IEEE Transactions on Computers
Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses
IEEE Transactions on Computers
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
IEEE Transactions on Computers
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Proceedings of the 45th annual Design Automation Conference
Application-specific Processor Architecture: Then and Now
Journal of Signal Processing Systems
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
IEEE Transactions on Computers
Circle-Representations of simple 4-regular planar graphs
GD'12 Proceedings of the 20th international conference on Graph Drawing
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In this paper, we use crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of computationally useful networks. In particular, we describe 1) an N-node planar graph which has layout area Θ(NlogN), and maximum edge length Θ(N1/2/log1/2N), 2) an N-node graph with an O(N1/2)-separator which has layout area Θ(Nlog2N) and maximum edge length Θ(N1/2logN/loglogN), and 3) an N-node graph with an O(N1-1/r)-separator which has maximum edge length Θ(N1-1/r) for any r ≥ 3.