The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Orthogonal Transforms for Digital Signal Processing
Orthogonal Transforms for Digital Signal Processing
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Computational Aspects of VLSI
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Computer
A Generalized Technique for Spectral Analysis
IEEE Transactions on Computers
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
IEEE Transactions on Computers
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
IEEE Transactions on Computers
| Hi-index | 14.98 |
This correspondence presents a linear systolic array for the implementation pf digital signal processing systems based upon matrix- vector multiplication algorithms where the matrix elements can be computed from their row and column indexes. Haar, Walsh, and the discrete Fourier transforms are solved using this approach. The method presented enables the n2 matrix elements to be computed in situ directly from the 2n matrix indexes. Thus, performance comparable to known systolic matrix-vector multipliers is achieved using only constant I/O bandwidth, rather than O(n) bandwidth required in the more general case. A generalized method is given for the development of recursively formed matrices and specifically the VLSI implementation of the Haar and Walsh transforms.