Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
A taxonomy of parallel sorting
ACM Computing Surveys (CSUR)
A model of computation for VLSI with related complexity results
Journal of the ACM (JACM)
Aspects of information flow in VLSI circuits
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers
Design of a Multiple-Valued Systolic System for the Computation of the Chrestenson Spectrum
IEEE Transactions on Computers
Tradeoffs for VLSI models with subpolynomial delay
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Provably good routing in graphs: regular arrays
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Evaluation of On-Chip Static Interconnection Networks
IEEE Transactions on Computers
Size-time complexity of Boolean networks for prefix computations
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
On the Time-Bandwidth Proof in VLSI Complexity
IEEE Transactions on Computers
On an Optimally Fault-Tolerant Multiprocessor Network Architecture
IEEE Transactions on Computers
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
Optimal VLSI circuits for sorting
Journal of the ACM (JACM)
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs
IEEE Transactions on Computers
Size-time complexity of Boolean networks for prefix computations
Journal of the ACM (JACM)
Energy consumption in VLSI circuits
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
IEEE Transactions on Computers
Optimal VLSI architectures for multidimensional DFT
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Extreme Area-Time Tradeoffs in VLSI
IEEE Transactions on Computers
The computational complexity of universal hashing
STOC '90 Proceedings of the twenty-second annual ACM symposium on Theory of computing
Separators in two and three dimensions
STOC '90 Proceedings of the twenty-second annual ACM symposium on Theory of computing
Upper and lower bounds on switching energy in VLSI
Journal of the ACM (JACM)
Optimal VLSI architectures for multidimensional DFT (preliminary version)
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Parallel Algorithms for Image Processing on OMC
IEEE Transactions on Computers
IEEE Transactions on Computers
Design of a highly reliable cube-connected cycles architecture
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Spatial machines: a more realistic approach to parallel computation
Communications of the ACM
Fast Algorithms for Routing Around Faults in Multibutterflies and Randomly-Wired Splitter Networks
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Designing interconnection networks for multi-level packaging
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
AT2 bounds for a class of VLSI problems and string matching
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay
IEEE Transactions on Computers
Deterministic on-line routing on area-universal networks
Journal of the ACM (JACM)
Parallel sorting with limited bandwidth
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
A tight layout of the butterfly network
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
Mesh-Connected Trees: A Bridge Between Grids and Meshes of Trees
IEEE Transactions on Parallel and Distributed Systems
Efficient VLSI Layouts for Homogeneous Product Networks
IEEE Transactions on Computers
Some compact layouts of the butterfly
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
Graph Problems on a Mesh-Connected Processor Array
Journal of the ACM (JACM)
A new parallel multiplication algorithm and its VLSI implementation
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
Parallel VLSI computation of all shortest paths in a graph
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
Tighter Layouts of the Cube-Connected Cycles
IEEE Transactions on Parallel and Distributed Systems
VLSI layout and packaging of butterfly networks
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Communication complexity method for measuring nondeterminism in finite automata
Information and Computation
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Layout area of the hypercube: (extended abstract)
SODA '02 Proceedings of the thirteenth annual ACM-SIAM symposium on Discrete algorithms
On the area of hypercube layouts
Information Processing Letters
IEEE Transactions on Computers
IEEE Transactions on Computers
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
Reconfiguration and Analysis of a Fault-Tolerant Circular Butterfly Parallel System
IEEE Transactions on Parallel and Distributed Systems
Products of Networks with Logarithmic Diameter and Fixed Degree
IEEE Transactions on Parallel and Distributed Systems
On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Randomized Communication Protocols (A Survey)
SAGA '01 Proceedings of the International Symposium on Stochastic Algorithms: Foundations and Applications
Functional Inversion and Communication Complexity
CRYPTO '91 Proceedings of the 11th Annual International Cryptology Conference on Advances in Cryptology
Journal of Automata, Languages and Combinatorics - Third international workshop on descriptional complexity of automata, grammars and related structures
The effect of register-transfer design tradeoffs on chip area and performance
DAC '83 Proceedings of the 20th Design Automation Conference
Synchronizing large VLSI processor arrays
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Probabilistic analysis of a crossbar switch
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
A layout strategy for VLSI which is provably good (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Measuring energy consumption in VLSI circuits: A foundation
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
New layouts for the shuffle-exchange graph(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
The entropic limitations on VLSI computations(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A multiprocessor network suitable for single-chip VLSI implementation
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A minimum area VLSI network for O(logn) time sorting
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Multilayer VLSI Layout for Interconnection Networks
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
On the Bisection Width and Expansion of Butterfly Networks
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Packetized On-Chip Interconnect Communication Analysis for MPSoC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
A Mesh-Connected Area-Time Optimal VLSI Multiplier of Large Integers
IEEE Transactions on Computers
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
IEEE Transactions on Computers
Two VLSI Structures for the Discrete Fourier Transform
IEEE Transactions on Computers
A VLSI Network for Variable Size FFT's
IEEE Transactions on Computers
Dynamic Memory Interconnections for Rapid Access
IEEE Transactions on Computers
IEEE Transactions on Computers
A Layout for the Shuffle-Exchange Network with O(N2/log3/2N) Area
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
Area-time tradeoffs for universal VLSI circuits
Theoretical Computer Science
Integration, the VLSI Journal
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved data structures for the orthogonal range successor problem
Computational Geometry: Theory and Applications
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
IEEE Transactions on Computers
VLSI Sorting with Reduced Hardware
IEEE Transactions on Computers
Strong I/O lower bounds for binomial and FFT computation graphs
COCOON'11 Proceedings of the 17th annual international conference on Computing and combinatorics
The potential of on-chip multiprocessing for QCD machines
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Parceling the butterfly and the batcher sorting network
Theoretical Computer Science
New area-time lower bounds for the multidimensional DFT
CATS 2011 Proceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 119
Synthesis and array processor realization of a 2-D IIR beam filter for wireless applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.11 |